Project proposal - 1KB SRAM Chip Design
As a part of the coursework for the CSE 477 course, I am going to design, layout and verify a 1KByte Static Random Access Memory (SRAM) chip. In this project proposal, I have explained the basic organization and specifications of the SRAM chip. Details of the internal circuits, actual layout and the various size and timing specifications will be discussed in later reports.
Block Diagram and Explanation
Block Diagram of a One KiloByte Static RAM. (1024 * 8 bit) chip
The above diagram shows the structure of the SRAM. I will be using a Six transistor SRAM cell to store every bit. The total number of address lines needed for accessing the 1024 locations is ten. I have organized the SRAM into a 128 * 8 * 8 structure so as to make the final layout size more symmetrical. The total layout area permitted is 1800 * 1800 and so it makes sense to have a square layout instead of a rectangular layout.
Basic Building Blocks.
SRAM Cells: There will be a total of 8192 (128 * 8 * 8) SRAM cells. I will be using a six transistor SRAM cell to store every bit.
Row Decoder: This block will select one out of 128 rows of the SRAM cell array.
Column Decoder: This block will select one out of 8 columns of the SRAM cell array.
Sense amplifiers: They are used to increase the speed and decrease the power dissipation of the SRAM chip. The principle of operation and the circuits will be discussed later.
Data Control units: The I/P and O/P data control units will have tristate buffers and other components to process the data before it is written into the SRAM or is read out.
Control unit: It consists of simple combinational circuits, which generate the control signals for the Data control blocks. The inputs to the Control unit are CE (Chip Enable), WE (Write Enable) and OE (Output Enable) signals. These lines will be active low so as to make them compatible with standard devices.
SRAM Chip Specifications
Pin name |
Function |
|
A9 – A0 |
Address lines |
|
D7 - D0 |
Bi-directional Data lines. |
|
CE (Active low) |
Chip Enable |
|
WE (Active low) |
Write Enable |
|
OE (Active low) |
Output Enable |
|
Vdd, Gnd |
Power rails. |
System Block |
Number of transistors |
|
SRAM cells |
49152 |
|
Sense Amplifier |
320 |
|
Row Decoder |
1038 |
|
Column Decoder |
38 |
|
Control unit |
Approx 20 |
|
Data I/O control units |
Approx 92 |
|
Pre-charge + Miscellaneous |
320 + 30 |