Sub-cell Specifications.

SRAM cell

Sense Amplifier

SRAM Integrated!

Row Decoder

Column Decoder

Input Data Control

Output Data Control

Control circuitry.

Block Diagram of the entire SRAM chip.

Important Specifications: One KByte Static RAM chip using 6T SRAM cell. Organized as 128 * 8 * 8 SRAM cells Target Data Access time : < 15 ns. Approximate Transistor count: 51,000 Total I/O lines: 23 Pin name Function A9 – A0 Address lines D7 - D0 Bi-directional Data lines. CE  (Active low) Chip Enable WE (Active low) Write Enable OE  (Active low) Output Enable Vdd, Gnd Power rails. .

Chip function: The One KByte SRAM chip is capable of storing and retrieving data. The capacity of the chip is One KByte (8092 bits). The chip uses a total of 23 pins on the pad frame and is made up of approximately 51,000 transistors. Our objective is to keep the access time of the chip below 15 ns.

The above diagram shows the structure of the SRAM. I will be using a Six transistor SRAM cell to store every bit. The total number of address lines needed for accessing the 1024 locations is ten. I have organized the SRAM into a 128 * 8 * 8 structure so as to make the final layout size more symmetrical. The total layout area permitted is 1800 * 1800 and so it makes sense to have a square layout instead of a rectangular layout.

We have simulated all the basic building blocks using IRSIM / HSPICE. It is not possible to simulate all the blocks together due to a number of reasons. However, all the basic builiding blocks are working as expected and so we are confident that the final chip will function perfectly.

To summarize the work we have done till now, we would like to say that the entire system is ready for Layout design using Max Layout editor. Also, since some of the sub-cells have been verified using MAX, it will reduce some of the workload in the next task. 

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