COLUMN DECODER

The circuit diagram of the column decoder was shown in the specifications part and the working was also explained there. Please refer to the Specifications for details of the working of the column decoder. We will be concentrating on the MAX layout and timing issues here. The SRAM memory chip is organized as 128 rows * 8 columns, each column containing eight bits (one byte).

Name	Column Decoder.(multiplexer)
Inputs	3 bit address: A2, A1, A0 Pre-charge signal: p
Outputs	8 select lines: D0 – D7
Size	*35.67 64.24**
Time Delay	1 ns worst case.

We have used a dynamic NOR decoder for our project. This structure reduces the number of transistors by half. It also increases the speed of the decoder and makes the layout simple and less time-consuming. The structure of the column decoder is similar to the row decoder.It is evident that the outputs of the 3:8 decoder go to the outputs of the sense amplifier to multiplex the data. The selected line will assert the 8 bits coming from the SRAM memory cells and the sense amplifiers. So there will be 8 lines driving 8 lines each … corresponding to the 64 columns of SRAM cells.

The first picture shows the MAX layout of the 3:8 column decoder (multiplexer). The second picture shows a detailed image of the layout of the column deocder. If you contrast this with the row decoder, you will observe that the size of the address buffers is smaller. This is because the address lines need to drive only four lines each. So their current handling capacity does not need to be as high as is the case with the row decoder.

The pre-charge buffer is large, because it is required to drive 8 transistors. An additional NMOSFET has been provided to prevent the circuit to be grounded, when the pre-charge is going ON. This is required for proper pre-charge on all the lines.

Simulation and results

The figure above shows the simulation waveforms for the decoder. You can observe that, when the pre-charge input is asserted (p = ‘0’), all the outputs go high. The 3-bit address is also present on the address lines. As soon as the pre-charge line goes high, the ground line is connected and all the output lines, except the one selected by the address go to logic zero.

The simulation waveform shows four different cases. We also tested the other four combinations but only four are shown on the waveform to make it more understandable. The results have been summarized in the table below.

The second set of simulation results show a Zoom-in view of the waveforms. Here we are trying to approximate the delay of the decoder. Please note that we are not measuring the “propagation delay” of the output at 50% voltage level. Once the pre-charge signal is de-asserted, the outputs of the decoder take a finite time interval to go back to logic ‘0’. All, except one of the output will go back to zero volts. Only after the 7 lines have gone back to zero volts, we should consider the output of the column decoder valid.

We are measuring this time interval. The control circuitry needs to be modified accordingly to take care of the delay. This time delay has been found to be 0.86 nano seconds in the worst case. It is interesting to note that the worst-case delay will be on the addresses which have only one ‘1’ in it…i.e. 001, 010 & 100. This is because, in these cases, during the evaluation phase, there is only one path for the capacitor to discharge to ground and so the node takes more time to discharge the capacitor.

We have designed the control circuitry, to take care of a delay of 1 ns or probably even more, so as to provide a safety margin, just in case there are any abnormal operating conditions and the decoder takes more time to settle down. The final delays in the control circuitry will be fixed in the last phase of optimizing and fine-tuning the system.

The column multiplexer, row decoder and the SRAM cells have been tested together. We have succeeded in writing a byte of data to a particular location and reading it back. Those things have been explained separately.

A2	A1	A0	Outputs
0	0	0	D0 goes high and other lines go low.
0	0	1	D1 goes high and other lines go low.
0	1	0	D2 goes high and other lines go low.
1	1	1	D7 goes high and other lines go low.