Control Logic Circuit: Go to Specifications page.

The circuit diagram of the Control Logic was shown in the specifications part and the working was also explained there. Please refer to the Specifications for details of the working of the control logic circuit. We will be concentrating on the MAX layout and timing issues here. Each SRAM will be used for storing a single bit of data on the memory chip.

Basic Specifications:

The control logic circuit takes three inputs – CE, OE, and WE (all active low), and outputs four signals – PCM, PCD, SE, and OR – that are used internally in the chip.

These signals are used to control the Memory Array, Row and Column Decoders, I/O Control Logic, and Sense Amplifiers.

The sequence and timing are two main issues in designing the control logic circuit.  The sequence in which these signals shall be asserted was determined and documented in the Specifications Document.

The time that each of these signals should stay on is still variable and will be finalized during the final stage of our design (Tuning and Reducing the delay).

Below is the MAX Layout of the Control Logic Circuit. This is the heart of the chip which controls all the other components. The colors in the picture below have been altered to keep our control logic secret. :-) 

Simulation and results

The figure above shows a simulation of preliminary control logic.  Six cycles have been simulated, in the following order.

            *CE signal is assumed low for this simulation.

 As already mentioned, the timing here is picked to make sure that every Read/Write operation completes.  Every pulse length will be minimized at the final stage of the design to minimize the overall Read/Write Cycle length.

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