INPUT DATA CONTROL BLOCK: TOTAL LAYOUT.
INPUT DATA CONTROL BLOCK: ZOOM IN TO SINGLE ELEMENT.
INPUT DATA CONTROL BLOCK : Go to Specifications page.
The circuit diagram of the Input Data Control Block was shown in the specifications part and the working was also explained there. Please refer to the Specifications for details of the working of the Input Data control block. We will be concentrating on the MAX layout and timing issues here.
Basic
Specifications:
|
Name |
Input Data Control Block |
|
Inputs |
8 bit data: I7 -- I0 Write Enable: we |
|
Outputs |
8 bit data: BL7 – BL0 |
|
Size |
8.54 * 85.79 |
|
Time Delay |
Approx 102 pico seconds. |
|
INPUT DATA CONTROL BLOCK: TOTAL LAYOUT. |
INPUT DATA CONTROL BLOCK: ZOOM IN TO SINGLE ELEMENT. |
The MAX layout(s) of the input data control block is as shown ABOVE. The input data control block is basically just a data routing block. Data from the I/O pins is passed into the block and then transferred to the memory cell array via a buffer circuit and a pass-transistor. The pass-transistor controls the flow of data into the memory cell array.
 |
INPUT DATA CONTROL BLOCK: ANOTHER PICTURE. |
The picture above shows another zoom-in view of the
Input Data control block. This is a very simple circuit and does not require
more simplification Basically, during a write cycle, the write enable line (webar)
will be low which in turn will close the pass-transistor via an inverter gate.
Likewise, during the read cycle this pass-transistor will be open to prevent
data from entering the memory cell array.
The two inverters before the pass-transistors are
basically buffers, used to increase the current handling capacity of the input
data control block. The output lines of this block will have to travel a long
distance and so it really helps to increase the current capacity of the buffers
and the pass-transistors. This will finally have a direct bearing on the speed
of the chip.
The webar control signal will be generated by the control circuitry, which has been explained separately.
Simulation and Results.
The picture above shows the waveforms of the circuitry. It can be observed that when the “we” signal (Write enable -- which is active low) is asserted, the output follows the input. In other words, all the latches are transparent and the output is the same as the input.
The second set of simulation waveforms shows the zoom-in view of the waveforms. The propagation delay of the circuit, which is measured from 50% level of the “we” signal to the 50% level of the resultant change in the output signal (if a signal transition is needed) is as shown. It can be seen that the delay of the circuit is about 102 pico seconds. The delay will be same for all the bits.