OUTPUT DATA CONTROL BLOCK: Go to Specifications Page

The circuit diagram of the Output Data Control Block was shown in the specifications part and the working was also explained there. Please refer to the Specifications for details of the working of the Output Data control block. We will be concentrating on the MAX layout and timing issues in this report.

 Basic Specifications: 

OUTPUT DATA CONTROL CIRCUITRY: TOTAL LAYOUT.

The MAX layout of the input data control block is as shown above. The output control block is a simple controlled buffer circuit. A tri-state inverter is used to control the flow of data to the I/O pins from the SRAM cells, which holds the actual data. When the output enable line (OE) is high, the data from the memory array cell can be read to the output. When the output enable line is low, the tri-state inverters will turn off and prevent data on the I/O lines inside the chip from going to the external data bus. This is important because the data lines are bi-directional and we don’t want any kind of signal mix-up between the data going in the chip and data coming out of the chip.

OUTPUT DATA CONTROL CIRCUITRY: ZOOM IN VIEW.

There is another zoom-in view of the circuit (shown above), which shows a single cell of the circuit. It is a very simple circuit and the working is evident, even from the layout. The inverting tri-state buffer is preferred over the non-inverting tri-state buffer because it saves us some gates. The inverter is used before the tri-state buffer to invert the signal so as to get the right data at the output.

The output enable line was added to provide fast memory access. This can occur when the memory address can be provided before the data needs to be accessed. When the data is ready for reading, the user only needs to activate the output enable line (OE) and the data will be sent from the output control buffer to the I/O pins. This will result in a drastic timesaving by cutting the access time approximately by half.

 SIMULATION AND RESULTS.

From the simulation waveforms shown above, you can observe that the output follows the input when the “oe” control signal is asserted. When this signal is de-asserted, the output goes to the high-impedance state. Basically the capacitor at the output will retain the charge and the lines will retain their previous states.

We had actually done the max layout of this block before because it was not possible to simulate it in IRSIM. So now, we just optimized the layout for minimum area.  The second simulation result shows the zoom-in view of the waveforms of the circuit. It can be seen that the propagation delay of the circuit, which is basically the time difference between the 50% level of the “oe” signal and the 50% level of the output signal is about 86.9 pico seconds. This is a very small circuit and so the delay is very less. Moreover the delay will be the same for all the cases.

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