ROW DECODER

ROW DECODER: Go to Specifications Page.

The circuit diagram of the column decoder was shown in the specifications part and the working was also explained there. Please refer to the Specifications for details of the working of the column decoder. We will be concentrating on the MAX layout and timing issues here. The SRAM memory chip is organized as 128 rows * 8 columns, each column containing eight bits (one byte).

Basic Specifications:

Name	Row Decoder.
Inputs	7 bit address: A6 -- A0 Pre-charge signal: p
Outputs	128 select lines: D0 – D127
Size	*69.93 508.4**
Time Delay	3 ns worst case.

We have used a dynamic NOR decoder for our project. This structure reduces the number of transistors by half. It also increases the speed of the decoder and makes the layout simple and less time-consuming. The structure of the row decoder is similar to the 3 to 8 column decoder and it is a better idea to first understand the working of the 3 to 8 decoder and then extend the same concept for the 7:128 row decoder. It is evident that the outputs of the 7:128 decoder go to the rows of the SRAM cells in the actual memory block. The selected line will assert the word line of one of 128 rows of SRAM cells, each containing 64 SRAM cells.

ROW DECODER : TOTAL LAYOUT.

ROW DECODER : PRECHARGE BUFFER + NMOS TRANSISTORS TO SELECT LINE

The diagram on the left side above shows the max layout of the 7:128 row decoder. The other picture shows detailed images of the layout of the Row decoder.

ZOOM-IN VIEW OF THE ROW DECODER SHOWING THE ADDRESS BUFFERS.

The picture above shows the zoom-in view of the Buffers. You can observe the large size of the Address Buffers.

This is needed for the following two reasons:

The address lines are required to drive 64 transistors each. The input capacitance of all these transistors will add up and so a lot of current will be needed to drive them, without compromising on the speed.
The address lines are connected using poly, which has very high resistance. The buffering needed would have been less, if we had used metal to make those connections. However, that would have increased the area (because of vias) and more importantly caused some cross connections. Finally there was a trade-off and we decided to proceed this way.

The pre-charge buffer is also large, because it is required to drive 128 transistors. An additional NMOSFET has been provided to prevent the circuit to be grounded, when the pre-charge is going ON. This is required for proper pre-charge on all the lines.

Simulation and Results

The figure above shows the simulation waveforms for the decoder. You can observe that, when the pre-charge input is asserted (p = ‘0’), all the outputs go high. The 7-bit address is also present on the address lines. As soon as the pre-charge line goes high, the ground line is connected and all the output lines, except the one selected by the address go to logic zero.

This simulation waveform shows six different cases:

A6	A5	A4	A3	A2	A1	A0	Output
0	0	0	0	0	0	0	D0 high, all other lines low.
0	0	0	0	0	0	1	D1 high, all other lines low.
0	0	0	0	0	1	1	D3 high, all other lines low.
0	0	0	0	0	1	0	D2 high, all other lines low.
1	1	1	1	1	1	1	D127 high, all other lines low.
1	1	1	1	1	1	0	D126 high, all other lines low.

We also tested some random addresses in between and the system works perfectly.

The second set of simulation results (above) show a Zoom-in view of the waveforms. Here we are trying to approximate the delay of the decoder. Please note that we are not measuring the “propagation delay” of the output at 50% voltage level. Once the pre-charge signal is de-asserted, the outputs of the decoder take a finite time interval to go back to logic ‘0’. All, except one of the output will go back to zero volts. Only after the 127 lines have gone back to zero volts, we should consider the output of the row decoder valid.

We are measuring this time interval. The control circuitry needs to be modified accordingly to take care of the delay. This time delay has been found to be 2.91 nano seconds in the worst case. It is interesting to note that the worst-case delay will be on the addresses which have only one ‘1’ in it…e.g. 0000001, 0000010 … 1000000. This is because in these cases, during the evaluation phase, there is only one path for the capacitor discharge to ground and so it takes more time.

We are going to design the control circuitry, to take care of a delay of 3 ns or probably even more, so as to provide a safety margin, just in case there are any abnormal operating conditions and the decoder takes more time to settle down.

The column multiplexer, row decoder and the SRAM cells have been tested together. We have succeeded in writing a byte of data to a particular location and reading it back. Those things have been explained separately.

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