Sense Amplifier: Go to Specification page

The circuit diagram of the Sense Amplifier was shown in the specifications part and the working was also explained there. Please refer to the Specifications for details of the working of the column decoder. We will be concentrating on the MAX layout and timing issues here.  A sense amplifier will amplify a signal coming off the Bit Lines during a Read sequence.

 Basic Specifications:

 As described in Specifications Page, we are using a Cross-coupled Sense Amplifier to sense a difference of two incoming voltages and give two full swing outputs. 

In order for the Sense Amplifier to give correct output, the input voltages need to have a certain (small) voltage difference.  This difference shall be determined in this section.  We need to make sure that in the worst case scenario the voltage difference will not be below the accepted one.

Below is a MAX layout of a Cross-coupled sense amplifier.

Please note that after running several tests, it was determined that the overall circuit could work without using Sense Amplifiers.  That is - the Bit Lines eventually will reach full swing output without amplification.  But further tests indicated that the overall time delay associated to a read cycle would be reduced by 2 – 5 ns if Sense Amplifiers were used.  As we mentioned in SRAM cell section, we were very pleased with amount of space the memory array will take on the chip, meaning that we are not “pressed” for space.  With this in mind, it makes sense to use Sense Amplifiers in our design to decrease the delay time.

Simulation and results

We will go through six simulations of the Sense Amplifier and will derive the results at the end of this section.

Simulation 1.

The figure above shows a simulation of a Sense Amplifier with Bit Lines swinging from 1.5 - 1.7V.  Two cycles have been simulated, in the following order.

·        Note:  Associated Delay means:

o       Read Cycle – Time required for data to appear on Y and Ybar after SE has been set to 1.

As you can see, the Sense amplifier worked, the outputs came out full swing 0 –  2.50V.

Simulation 2.

The figure above shows a simulation of a Sense Amplifier with Bit Lines swinging from 2.2 - 2.5V.  Two cycles have been simulated, in the following order.

·        Note:  Associated Delay means:

o       Read Cycle – Time required for data to appear on Y and Ybar after SE has been set to 1.

 As you can see, the Sense amplifier did not work with these input conditions.

Simulation 3.

The figure above shows a simulation of a Sense Amplifier with Bit Lines swinging from 2.0 - 2.5V.  Two cycles have been simulated, in the following order.

·        Note:  Associated Delay means:

o       Read Cycle – Time required for data to appear on Y and Ybar after SE has been set to 1.

As you can see, the Sense amplifier worked, the outputs came out full swing 0 – 2.50V.

Simulation 4.

The figure above shows a simulation of a Sense Amplifier with Bit Lines swinging from 0.3 - 1.0V.  Two cycles have been simulated, in the following order.

·        Note:  Associated Delay means:

o       Read Cycle – Time required for data to appear on Y and Ybar after SE has been set to 1.

 As you can see, the Sense amplifier worked, the outputs came out full swing 0 – 2.50V.

Simulation 5.

The figure above shows a simulation of a Sense Amplifier with Bit Lines swinging from 0.0 - 0.5V.  Two cycles have been simulated, in the following order.

·        Note:  Associated Delay means:

o       Read Cycle – Time required for data to appear on Y and Ybar after SE has been set to 1.

 As you can see, the Sense amplifier did not work with these input conditions.

The results of the above 5 simulations are put into the table below:

Several conclusions could be drawn from the above simulations:

·   Simulation 1 shows that input voltage swing could be small (200 mV), and the amplifier will work only if both voltages stay in the middle (between 1.0 V and 1.9V)

·   Simulations 2 & 5 show that when one of the input signals is at extreme end, the input swing must be larger than in simulation 1, and also the delay increases as the average of both inputs moves toward 0.0V or 2.5V

Based on all five simulations, we are ready to impose a restriction on the input voltage difference:

·   The voltage difference between two inputs – X and Xbar –must be 0.7 V or larger in order to have the Sense Amplifier produce correct output.

·   No restrictions on the maximum/minimum input voltage are imposed, only on the difference.

Simulation 6.

Below is an HSpice simulation that led us to conclude that Sense Amplifier should after all be used in our design.

This simulation was recorded as part of testing the overall integrated SRAM circuit.

The reader should only pay attention at simulation between 20.0 and 50.0 ns.  That is when the READ Cycle is taking place.

BL0 and BLbar0 are Bit Line and Bit Linebar, that are pre-charged at the beginning of a read cycle.  After WL is pulled high, the content of a memory cell appears on the Bit Lines.

BL0 and BLbar0 are inputs into a Sense Amplifier, and Y0 is the output of the Sense Amplifier.

Two time delays are measured:

·   The time is measured from asserting a WL at 33.0 ns to when Y0 is available. 

·   The time is measured from asserting a WL at 33.0 ns to when the Bit Lines are available.

As you can see:

·   Read delay with Sense Amp = 3.59 ns

·   Read delay without Sense Amp = 5.35 ns

Thus, in the above simulation, the difference of using a Sense Amplifier makes a READ operation about 2 ns faster.  We believe that with further investigation and design, we will be able to use the Sense amplifiers to reduce the overall READ time by 5 ns.

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