SRAM Integrated:  Go to Specifications page

The circuit diagram of the overall Static RAM circuit could be found in the specifications part. Please refer to the Specifications for details of the working of the overall circuit. We will be concentrating on the MAX layout and timing issues here.  We are simulating two Read and two Write cycles on same 8 bits specified by the same address.  To simulate 8 bits of the SRAM circuit, we are using 1 row and 8 columns of the memory array.

 Basic Specifications:

                        * Will improve

The basic task at this point is to WRITE 8 bits at a specific memory address (where a row and 8 columns intersect), and then to READ the memory at the same address and to make sure that the previously written data was recorded and is read during the READ cycle.

Below is a MAX layout of the simulated SRAM circuit

 Worst Case Timing:

·  Write Operation: the worst-case timing delay will occur when we are writing 8 bits to the topmost row and to the rightmost 8 columns of the memory array.

·   Read Operation: the worst-case timing delay will occur when we are reading 8 bits from the topmost row and from the rightmost 8 columns of the memory array.

Simulation and results

To simulate the WRITE and READ cycles of the 8 bits of the SRAM circuit we need to include some outside circuitry in the form of a “dummy processor” in addition to the circuitry already present on the chip.  In the *.hsp file, you will find inputs ID7-ID0.  These 8 bits correspond to the “Input Data” that are sent by the dummy processor to the SRAM chip during the Write operation.

The address to which we are writing and from which we are reading will remain constant, thus the inputs to the Row and Column Decoders will also remain constant.  The only active inputs that will go into both decoders are the Pre-charge bits, which we will control manually for this simulation.

We will also control the Pre-Charge signal going to the Memory Array, and the Sense Amplifier Enable signal going to the Sense Amplifier.

Out of the three control signal: CE, OE, and WE, we will only use WE signal, which is active low.  We will not use the other two because they mainly deal with I/O control logic, and at this point we are not using I/O control logic because we only have 8 bits to simulate.

To sum up what is said above, here is the table of all the signals that go in and out of the SRAM circuit

* These signals are not shown on the HSpice simulation, they could be found in the .hsp file

** These signals are always constant, so there is no point of showing them on the HSpice simulation

The figure above shows a simulation of 8 bit of SRAM circuit.  Four cycles have been simulated, in the following order.

·        Associated Delay means:

o       Write Cycle: the time from which WE goes low to the time when WE goes high.

o       Read Cycle: the time from which the PCDC goes low to the time when the data is available on the output lines Y (7-0). (at this point this is the best way to measure the delay)

For the final design stage, we will only have A9-A0, D7-D0, CE, OE, and WE signals as inputs to the circuit, and have only D7-D0 as inputs/outputs (bi-directional).  We will simulate Read/Write operations for several addresses in the array.

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