SRAM Memory Cell

SRAM Memory Cell: Go to Specifications page.

The circuit diagram of the single SRAM cell was shown in the specifications part and the working was also explained there. Please refer to the Specifications for details of the working of the column decoder. We will be concentrating on the MAX layout and timing issues here. Each SRAM will be used for storing a single bit of data on the memory chip.

Basic Specifications:

Name	SRAM cell
Inputs	Word Line: WL
Inputs/Outputs	Bit Lines: BL & BLbar
Size	*5.230 7.730**
Time Delay	Read Operation: » 1ns Write Operation: » 2ns

Each SRAM cell will be connected to an adjacent SRAM cell by BL and BLbar, VDD, GND (vertically), and by WL (horizontally). A standard 6-transistor model was used, with minimal transistor sizing.

One of our primary objectives for this project is making the overall chip design as small as possible. The chip is mostly populated by SRAM cells; therefore we have put a significant effort into minimizing the cell. It is evident from the size of the cell that we have succeeded0 - the overall memory array takes about 335.0* 970.0 (mm), leaving us a LOT of space for other circuitry.

SRAM cell : LAYOUT.

Simulation and results

Additional circuitry was attached to a single SRAM cell in order to simulate it.

Signals found on the simulation results:

Signal Name	Explanation
BL & BLbar	Bit Line and Bit Line Inverted
WL	Word Line
WE	Write Enable (active high here). When enabled – a write operation is being performed.
P	Pre-charge (active low)
ID	Input Data – data that is to be written to the cell during a write cycle.

The figure above shows a simulation of a single SRAM cell. Three cycles have been simulated, in the following order.

Cycle	Time of Cycle on Hspice simulation	Associated Delay	Notes
Read	0 – 14 ns	0.532 ns	‘0’ is read on BL ‘1’ is read on BLbar
Write	20 – 40 ns	1.330 ns	‘1’ is written to BL ‘0’ is written to BLbar
Read	41 – 57 ns	0.465 ns	‘1’ is read on BL ‘0’ is read on BLbar

· Note: Associated Delay means:

o Read Cycle – Time required for data to appear on Bit Lines after WL has been asserted

o Write Cycle – Time required for data (available on Bit Lines) to be latched by the cell after WL has been asserted

More testing will be done on SRAM cells as they are combined to form a memory array.

Back to Project Prototype page

Word Line: WL

Bit Line and Bit Line Inverted