SmartDIMM
I/O Requirements (4/27/00)
<Direct
FPGA/PC100 Interface>
Remaining:
PAL
22LV10
Inputs
I/O
Signal names
Port
Inputs
I/O
22
10
Address Bus inputs
5
0
17
10
/S0, /S1, /CAS, /RAS,
/WE
CPLD Bank Enables
2
0
15
10
BE1, BE2
Bank 0 control
outputs
0
4
11
6
/OEA1_CPU, /OEB1_CPU,
/LEA1_CPU, /LEB1_CPU
Bank 1 control
outputs
0
4
7
2
/OEA2_CPU, /OEB2_CPU,
/LEA2_CPU, /LEB2_CPU
Free I/O Pins
7
2
CPLD
MAX7000A
100 pins
144 pins
Signal names
Port
Required pins
84
110
PC100 Interface
21
63
89
/S0, /RAS, /CAS, /WE,
A0-A13, CLK, /BA0, /BA1
PC100 Data
20
43
69
D0-D19
Address Buffers
4
39
65
Bank0_CPU, Bank1_CPU,
Bank0_FPGA, Bank1_FPGA
PAL Control
2
37
63
BE1, BE2
Configuration SRAM
28
9
35
S_D0-S_D7, S_CS,
S_A0-S_A18
Free I/O pins
9
35
FPGA
XCV300
240 pins
Signal names
Port
Required pins
166
SDRAM Interface
85
81
D0-D63, A0-A13, /S0,
/S1, /RAS, /CAS, /WE, /BA0, /BA1
Configuration
16
65
C_M0-C_M2, C_CS, C_WE,
C_INIT, C_PROG, C_CLK, S_D0-S_D7
32-bit PC100
Interface
52
13
/S2, /RAS, /CAS, /WE,
A0-A13, CLK, D0-D31, /BA0, /BA1
Free I/O Pins
13