SmartDIMM Control Register Address Space

 (revised 4/20/2000)

The CPLD/FPGA will occupy a 32MB address space on the SmartDIMM device.  This address space will be decoded by the CPLD or FPGA as “virtual” memory locations through which the CPU can control the SmartDIMM device and communicate directly with the FPGA.  To simplify address decoding, each register will be located in a separate 4K page.

The CPLD will occupy the first 16MB (256k locations) of the virtual address space, implementing the following registers:

1.            1.  STATUS - 8 bit, read-only located at 0000:0000

Reading this location gives an 8-bit result indicating the status of the SmartDIMM and the currently running FPGA application (if any).

Possible status flags:

• 0x00 -- READY: CPLD ready to accept a command

• 0x01 -- BUSY_RESET: CPLD is busy resetting FPGA configuration

• 0x02 -- BUSY_ACCESSCONTROL: CPLD is busy switching bank access

• 0x03 -- BUSY_CONFIG: CPLD is busy sending configuration data to FPGA

• 0x04 …

2.            2.  Command - 8 bit, write-only located at 0000:1000

Commands for the SmartDIMM are written to this register.

Possible commands:

• 0x00 – NOOP: do nothing

• 0x01 – RESET: reset FPGA configuration

• 0x02 – SEND_CONFIG: send configuration block to FPGA

• 0x03 – START_FPGA:  configuration of FPGA is finished, start FPGA

• 0x04 – SET_BANK1_ACCESS: Give CPU access to SDRAM bank 1

• 0x05 – SET_BANK2_ACCESS: Give CPU access to SDRAM bank 2

• 0x06 …

3.   CONFIG_ADDRESS – 20 bit write-only located at 0000:2000

      This register points to the location in the configuration SRAM which will be written by the next access to CONFIG_DATA. (20 bits = 1M addresses for a maximum of 1MB configuration memory size)

4.   CONFIG_BLOCK_SIZE – 20 bit write-only located at 0000:3000

      This register tells the CPLD the length of the next frame to be written to memory.  The block size can vary from one configuration frame (approx. 1Kb) to the full size of the SRAM to support full or partial configuration.  

5.   CONFIG_DATA - 8 bit write-only at 0000:4000

Data read/written to this register is transferred to/from the configuration SRAM at the location pointed to by CONFIG_ADDRESS.  Accesses to this memory location automatically increment the CONFIG_ADDRESS register to the next location.

6.  RESERVED – locations 0000:5000-0000:F000 are reserved and are currently ignored.