SmartDIMM Control Register Address Space

Previous Version; has summary of changes at the end of the document

(revised 4/7/2000)

Active Mode:

            When the SmartDIMM is in Active Mode, these registers will be visible in an address space separate from that of the physical SDRAM.  To conserve CPLD resources as much as possible, the number and width of the registers should be minimized as much as possible without constraining the performance of the interface.  The following registers are proposed:

1. STATUS – 8 bit, read-only located at 0000:0000h (row address 00000)

Reading this location gives an 8-bit result indicating the status of the SmartDIMM and the currently running FPGA application (if any).

Possible status flags:

•             0x00 – Ready (Active mode, application ready to execute)

•             0x01 – Free (Active mode, no FPGA application loaded)

•             0x02 – Loading data into configuration SRAM

•             0x04 – Loading configuration data from SRAM to FPGA

•             0x08 – Error in FPGA configuration (CRC error)

• 0x10 … 0x80 – Reserved

2. COMMAND – 8 bit, write-only located at 0000:1000 (row address 00001)

Commands for the SmartDIMM are written to this register.

Possible commands:

•             0x00 – No-Op

•             0x01 – Switch active banks

•             0x02 – Switch to Passive mode

•             0x04 – Reset/Deactivate FPGA

• 0x08 – Activate FPGA

• 0x10 – Send configuration frame to FPGA  

•              0x20 … 0x80 – Reserved

3. CONFIG_ADDRESS 8-bit write-only at 0000:2000 (row address 00010)

This register holds the address in the configuration SRAM that the next configuration data should be written to/read from.

4. CONFIG_DATA – 8 bit write-only at 0000:4000 (row address 00100)

Data read/written to this register is transferred to/from the configuration SRAM at the location pointed to by CONFIG_ADDRESS.  Accesses to this memory location automatically increment the CONFIG_ADDRESS registers to the next location.

5. Locations that map to the address space 0000:8000-0000:FFFF (row address 01xxx) are passed directly to the FPGA via a 16-bit bus.  The lower two bits of the address are also passed to the FPGA to enable it to distinguish between registers. The third bit is used to distinguish between read/write accesses (for a total of four read-only and four write-only registers).

6. Memory locations 0001:0000 and above are reserved for future use and are currently ignored by the CPLD.

Passive Mode:

            In the passive, mode, the FPGA is inactive and both banks of SDRAM are visible to the CPU and usable for application data.  The CPLD registers are still visible to a SmartDIMM-aware application.

Interface CPLD Requirements

This interface requires a total of 52 bits of externally available memory, plus internal state data.  The necessary I/O signals are:

• CLK – 100MHz system clock input

• /CS0-3, /WE, /RAS, /CAS – control inputs from PC100

• A0-A4 – address inputs from PC100

• D0-D15 – data inputs from PC100

• BA0, BA1 – data buffer control outputs to PAL

• /OE1_FPGA, /OE1_CPU, /OE2_FPGA, /OE2_CPU - address buffer control outputs

•             C_D0-C_D7  - data outputs to configuration SRAM

•             C_A0-C_A7 – address outputs to configuration SRAM

•             C_CS – chip select output (& write enable) for configuration SRAM

•             V_M0-V_M2 – Virtex configuration source control outputs

•             V_PROG – Virtex configuration reset output

•             V_INIT – Virtex reset complete / configuration error input

•             V_CS – Virtex configuration chip select (& write enable) output

• V_A0-V_A1 – Virtex I/O register select outputs

•             V_D0-V_D15 – Virtex I/O register data I/O

•             V_WE – Virtex I/O register write enable output

•             V_CS – Virtex I/O register chip select output

•             V_CLK – configurable rate FPGA clock output (<= 50MHz)

            -- for a total of 30 inputs, 34 outputs, and 16 I/O.

I/O Requirements:

            The Altera EPM7256AETC-100 CPLD has a total of 84 I/O pins, of which this interface uses 80, leaving 4 spare I/O pins.

Description of proposed modifications:

1)               The previous complete-configuration system has been replaced with a partial-configuration system in which configuration frames are sent to the SRAM and FPGA in single frames.  This allows less complex hardware and the option for partial reconfigurability at the expense of some CPU overhead.

2)               The previous set of semaphores has been replaced by a much more powerful communication system to allow the CPU to directly communicate to the FPGA without the necessity of switching banks.  This allows low-bandwidth, low-latency communication to the FPGA without the interruption of the currently operating program, simplifying several synchronization issues.  This has also reduced the memory requirements of the interface from 92 to 52 bits.  Commands that do not require CPLD operations, such as the FPGA START and HALT commands, are now send over this bus.

3)               The address map has been modified to allow complete decoding of the incoming register address at the RAS stage of the memory access, allowing several extra cycles of processing time.  This will simplify the CPLD design and provide a larger timing margin, at the expense of reducing the number of addressable locations.

4)               The width of the data bus has been increased to 16 bits to increase the direct bandwidth to the FPGA.  This increases the pin requirements of the interface, but within the limits of the specified CPLD.

5)               Configuration data readback has been removed from the interface.  As the total size of the configuration frame is only approximately 1Kbit, error checking is much less vital than in the previous 4Mbit design.  The FPGA contains internal CRC checking to prevent loading of incorrect data.

6)               Commands and status flags have been changed to a “one-hot” encoding to simplify the CPLD design.  This simplifies and accelerates the CPLD operation.  If more than 8 commands/status flags are needed, the registers can be extended up to 16 bits without changing the encoding.

7)               The SmartDIMM register space was moved from the existing SDRAM address space to a separate address space to work around issues of how the operating system maps physical memory.  Verification will have to be done as to how/if this can be implemented in the current hardware design.

8)               Because of operating system limitations, kernel data loaded into the SmartDIMM memory at bootup cannot be relocated.  This means that the SmartDIMM device cannot be booted up in passive mode and then switched to active mode without requiring the PC to reboot.  Workaround: is it possible for the OS driver to switch the SmartDIMM into passive mode after bootup, allowing application data (which is pageable) to use the SDRAM on the SmartDIMM until it is needed by the SmartDimm-aware application?