This is a sample waveform showing a read access.  All signals are sampled on the rising edge of the clock, and the clock period is 10ns (The timestamp data is not saved in the oscilloscope waveform file).  The first rising edge at the far right side is not a command.  The second rising edge is a valid command – the chip select (/S0) line is low.  This is the ACTIVE command – the /RAS signal is asserted at this time (not shown – only 4 channels can be captured at one time).  On the next rising clock edge, the /CAS line and the address lines are asserted, but the chip select is high so the SDRAM is inactive.  On the fourth rising edge, the chip select is low so the SDRAM starts the READ command.  Three cycles later (the last rising clock edge in the graph), the first data is read back from the SDRAM.